Placeholder article entry for technical notes on RTL design and VLSI flows.
#hardware#rtl#Philosophy
PRASHANT BAGRI
RTL Design Engineer & MTech Student @ IIIT Delhi
MTech student in Electronics and Communication Technology at IIIT Delhi working in RTL design, embedded systems, and neuromorphic computing research.
[CURRENT FOCUS]
RTL Design, Design Verification and Embedded Systems
[NAVIGATION]
[PROJECTS & RESEARCH]
ALL PROJECTS (3) →OAI333 Logic Design and Analysis (Static vs Dynamic Logic)
GUIDE: DR. ANUJ GROVER
Transistor-level OAI333 gate designed and verified in both static CMOS and dynamic logic styles — schematic capture, DRC/LVS-clean layout, post-layout extraction, and timing validation in Cadence Virtuoso.
Cadence VirtuosoStatic CMOSDynamic LogicMonte Carlo
Two-Stage CMOS Operational Amplifier
GUIDE: DR. S.S. JAMUAR
Designed and simulated a two-stage CMOS op-amp in Cadence Virtuoso: ~60 dB DC gain, ~5 MHz gain-bandwidth product, >60° phase margin, 1.8–2.5V supply.
Cadence VirtuosoAnalog CMOSCircuit Simulation
Neural Networks using Magnetic Tunnel Junctions (MTJ) for Neuromorphic Computing
GUIDE: DR. ANUJ KUMAR
Researched MTJ-based neuromorphic architectures — crossbar in-memory neural network acceleration, stochastic switching behavior, quantized weight storage, and energy-efficient ANN/CNN hardware mapping.
MTJNeuromorphic ComputingPythonPyTorchIn-Memory Computing